DV Engineer

Job Title	Design Verification Engineer (New Grads Welcome)
Post Date	01/24/2011
Job Area	Engineering - Hardware
Location	Canada - Markham
Job Function	Be a part of the Design Verification Team responsible for all the verification activities of Next Generation Multimedia Subsystems embedded in Mobile Phone and Tablet Processors and SOCs. Candidate will learn details of a complex embedded multimedia system, including the functionality of all the building blocks, overall system architecture and performance, power profiling and customer usecases. Gain exposure to and participate in further developing and enhancing leading edge HW Design and Verification processes and methods.
Skills/Experience	1.Detail oriented with strong analytic and debugging skills. 2.Strong communication skills (written and verbal) 3.Strong knowledge of Object Oriented programming (OOP). 4.Good working experience with C/C++. 5.Experience in one or more of the following is preferred: Hardware verification languages (HVL): Vera, SystemVerilog testbench and SystemC Hardware description languages (HDL): VHDL, Verilog and SystemVerilog 6.Knowledge in one or more of the following disciplines is preferred: fundamental knowledge of ASIC architecture, CPU (ARM v7, Cache, MMU, security, etc.), graphics (OpenGL ES, OpenVG, etc.), video (H.264, H.263, VC-1, etc.), audio (MP3, MIDI, etc.), display (MIPI DSI, HDMI), camera (CSI, ISP),bus interface and protocol (AHB, AXI), memory sub-system Quality of Service principles 7.Strong knowledge of digital circuits and event-driven simulators 8.Knowledge of Perl, tcsh, and GNU Make would be a strong asset 9.Working knowledge of system OS (Unix, Linux, Windows, etc.)
Responsibilities	1.Design verification during the pre-silicon phase of next generation ASIC development at core, subsystem and chip level through; Simulation (C/RTL) using directed and pseudo random tests Emulation (FPGA) using diagnostic suites 2.Test plan development, implementation, execution and closure in partnership with the ASIC teams. 3.Creating/maintaining test benches, assertions, monitors, functional coverage models, protocol checkers, test library and APIs 4.Working with the Performance Modeling team to correlate the capabilities of the RTL designs and the associated performance models 5.Developing and implementing verification infrastructures, tools and flows to continuously improve efficiency and automate the design verification processes. 6.Participate in a variety of verification and debug activities throughout the ASIC development cycle (pre and post-silicon). 7.Coverage analysis, power state analysis, Error report generation and tracking
Education Requirements	Required: Bachelor's in Computer Engineering, Computer Science, Electrical Engineering or related field of study Preferred: Masters